In the manufacture of circuitized semiconductor carrier structures, a dielectric sheet material is employed as the substrate. A conductive circuit pattern is provided on one or both of the major surfaces of the substrate.
A conductive pattern can be formed on the surface of the substrate using a variety of known techniques. These known techniques include the subtractive technique, where a layer of copper is etched to form the desired circuit pattern, the EDR (electroless direct bond) technique, where copper is electrolessly plated directly on the surface of the substrate in the desired pattern, and the peel-apart technique, where the desired circuit pattern is plated up from a thin layer of peel-apart copper.
If it is desired to use the EDB technique, it is necessary to plate directly on the surface of the substrate.
Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate must be seeded or catalyzed prior to the deposition of metal onto the substrate.
The electroless plating of copper onto a substrate is well-known in the art. For instance, an electroless or autocatalytic copper plating bath usually contains a cupric salt, a reducing agent for the cupric salt, a chelating or complexing agent, and a pH adjustor. In addition, if the surface being plated is not already catalytic for the deposition of the desired metal, a suitable catalyst is deposited onto the surface prior to contact with the plating bath. Among the more widely employed procedures for catalyzing a surface is the use of stannous chloride sensitizing solution and a palladium chloride activator to form a layer of metallic palladium particles.
Although the technology relative to electroless copper plating is continually being improved, there still remains room for additional improvement. Certain problems are specially pronounced when preparing structures having very fine line (down to 0.5 mil lines and 0.5 mil spaces) circuitization. The fine features typically have only been created for very short distances and only when needed for escaping a tight grid (down to 0.5 mm) pitch. Several problems currently exist that prohibit using thin film circuitization for global wiring on, for instance, rigid PWB (printed wire board).
The main problems are adhesion of the copper circuit to the laminate over long lengths (one inch or greater), insulation resistance between circuits as lines per channel increase, cross-sectional area of the circuits are limited with current techniques so that resistance losses prevent global wiring and use of current techniques is limited for build-up layers.